1. Field of the Invention
This invention relates to a technology mapping apparatus for a CMOS-LSI combination circuit configured by a logic circuit automatic synthesis technology.
2. Description of the Related Art
Automatically synthesizing a CMOS-LSI combination circuit requires a technology which not only reduces the number of gates but also enables the respective circuit elements in a combination circuit to be mapped to actually realizable gate cells (or simply cells below). This technology is referred to as technology mapping.
Technology mapping maps, through appropriate transformation, the respective circuit elements of a combination circuit to a plurality of actually realizable cells prestored in a cell library.
The conventional art of technology mapping is as follows: First, a combination circuit is expressed by a graph of a NAND circuit (NAND) or NOR circuit having two (2) input terminals and an inverter (INV). This is the case for all patterns stored in the cell library. By searching the respective circuit elements in a combination circuit for matching graphs in the cell library, the mapping technology causes the circuit elements to be mapped to the matched cell.
However, since the above prior art needs to have a cell library which stores the graphs corresponding to all possible patterns formed as respective circuit elements, it is disadvantageous because the cell library must store a huge volume of data and the matching step requires a huge processing volume.
When a graph matches with a NAND cell having five (5) input terminals, for instance, the graph also matches with NAND of cells having four (4), three (3) and two (2) input terminals. Therefore, when a cell has mores than two (2) input terminals, the same path in the cell library is searched multiple times. This causes a problem in that the matching process becomes very inefficient.
Furthermore, since the cell library has plural kinds of cells which match the respective circuit elements, the combination circuit having the minimum number of gates must be found among all possible combinations of cells to which respective circuit elements are mapped. Hence, a problem arises in that the processing volume becomes enormously large.